Designs with Error Correction Coding (ECC) Do Not Work After Subsequent Reset - Designs with Error Correction Coding (ECC) Do Not Work After Subsequent Reset Description Some designs with ALTMEMPHY-based DDR, DDR2, or DDR3 SDRAM high-performance controllers do not work with the Enable Error Detection and Correction Logic option turned on. This issue affects all designs that use DDR, DDR2, or DDR3 SDRAM high-performance controllers with the Enable Error Detection and Correction Logic option turned on. Your design does not work properly in both simulation and hardware after the subsequent reset. Resolution None. This issue will be fixed in a future version. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 10.0 10.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']