How do I disable PLL clock outputs being applied to registers in my design when the PLL is not yet locked? - How do I disable PLL clock outputs being applied to registers in my design when the PLL is not yet locked? Description To disable the PLL output clock from driving the registers in your design when the PLL is not locked, connect the input of the Clock Control (ALTCLKCTRL) block to the PLL clock output(s) as shown in Figure 1. The output of the ALTCLKCTRL block should then be connected to your registers. Use the Locked signal from the PLL to enable the output of the ALTCLKCTRL block. The output clock from the ALTCLKCTRL block is then enabled only when the PLL is locked. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']