Why do a small number of GND pins in the pin-out files of Stratix V, Arria V or Cyclone V devices have IO bank designations, whilst the rest do not? - Why do a small number of GND pins in the pin-out files of Stratix V, Arria V or Cyclone V devices have IO bank designations, whilst the rest do not? Description GND pins that have bank designations in the pin-out files of Stratix® V, Arria® V or Cyclone® V devices are defined as Programming Ground pins. They should be treated like all other GND pins on the device. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']