Error: VHDL error at auk_dspip_roundsat_hpfir.vhd(103): value "4294967295" is outside the target constraint range (-2147483848 to 2147483647) - Error: VHDL error at auk_dspip_roundsat_hpfir.vhd(103): value "4294967295" is outside the target constraint range (-2147483848 to 2147483647) Description Due to a problem in the Intel® Quartus® Prime Pro Edition software version 19.2, the error above can be seen when the output width of the FIR II Intel® FPGA IP is greater than or equal to 32 bits in rounding mode. Resolution To work around this error in existing software, set the IP parameter " Output LSB Rounding " to " Truncation ", or still use " Rounding ", but ensure that the output width is smaller than 32 bits. This problem has been fixed starting with the Intel® Quartus® Prime Pro Edition software version 20.1. Custom Fields values: ['novalue'] Troubleshooting 1507660634 False ['FIR II IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 20.1 19.2 ['Agilex™ 7 FPGAs and SoCs', 'Arria® 10 FPGAs and SoCs', 'Cyclone® 10 FPGAs', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']