why you get Error (12002): Port "clock"/"reset" does not exist in macrofunction remote update IP when generate remote update IP? - why you get Error (12002): Port "clock"/"reset" does not exist in macrofunction remote update IP when generate remote update IP? Description Due to a problem in Quartus Prime Version 16.1.0 Build169, you will see Error (12002): Port "clock" does not exist in macrofunction remote update and Error (12002): Port "reset" does not exist in macrofunction remote update when you instante a Altera Remote Update IP in your design and compile it. This is because ports in **_inst.v file clock and reset are different from macro module **_altera_remote_update_161_umq4nxq, which are defined as clock_clk and reset_reset. Resolution you can redefine the ports clock and reset in your design to clock_clk and reset_reset, then recompile. for example: rsu_a10 u_rsu_a10 ( .clock_clk (inclk), // clock.clk .reset_reset (reset), // reset.reset .avl_csr_write (avl_csr_write), // avl_csr.write .avl_csr_read (avl_csr_read), // .read .avl_csr_writedata (avl_csr_writedata), // .writedata .avl_csr_readdata (avl_csr_readdata), // .readdata .avl_csr_readdatavalid (avl_csr_readdatavalid), // .readdatavalid .avl_csr_waitrequest (avl_csr_waitrequest), // .waitrequest .avl_csr_address (avl_csr_address) // .address ); Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 16.1 ['Arria® 10 GT FPGA'] ['novalue'] ['novalue'] ['novalue']