Why doesn't the watchdog timer increment even after starting it? - Why doesn't the watchdog timer increment even after starting it? Description There is an issue with Qsys in the Quartus® II software versions 11.x when configuring the interval timer as a watchdog. The chip select signal is not connected. This will be fixed in a later version of the Quartus II software. As a workaround, edit the top level verilog file that Qsys generates. Search for the watchdog component. Tie off the chip select input signal to the interval timer to a 1'b1. timer_sys_timer_0 timer_0 ( .clk (clk_clk), // clk .reset_n (~rst_controller_reset_out_reset), // reset_n .address (timer_0_s1_agent_m0_address), // address .writedata (timer_0_s1_agent_m0_writedata), // writedata .readdata (timer_0_s1_agent_m0_readdata), // readdata .chipselect (1'b1), // chipselect .write_n (~timer_0_s1_agent_m0_write), // write_n .resetrequest (), // resetrequest .irq (timer_0_irq_irq) // irq ); Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']