Error(21843): Rule: gdrb_gdr_pcie_ip16::pf0_pci_msi_64_bit_addr_cap_rule @ gdr.z1577b.u_pcie_ss.u_ctop.ub_core16 - Error(21843): Rule: gdrb_gdr_pcie_ip16::pf0_pci_msi_64_bit_addr_cap_rule @ gdr.z1577b.u_pcie_ss.u_ctop.ub_core16 Description Due to a problem in the Quartus® Prime Pro Edition Software version 22.4 and earlier, the compilation error above occurs when the Multi-Channel DMA FPGA IP for PCI Express* is configured with the "Enable MSI Capability" parameter disabled and "Enable MSI 64-bit Addressing" parameter enabled. Both of these parameters need to be disabled when disabling the MSI capability. Resolution To work around this problem, disable the MSI 64-bit Addressing parameter in the IP Parameter Editor by following the steps below: Enable the MSI Capability parameter to access the 64-bit Addressing parameter (Under PCIe Settings>MCDMA Settings) Uncheck the "Enable MSI 64-bit Addressing" parameter Uncheck the "Enable MSI Capability" parameter Regenerate the IP and recompile the design . This problem is fixed beginning with the Quartus® Prime Pro Edition Software version 23.1 Custom Fields values: ['novalue'] Troubleshooting 14018349866 False ['Interfaces'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.1 22.3 ['Agilex™ 7 FPGAs and SoCs', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']