Why is there no video data stream output using the DisplayPort FPGA IP when downtraining from UHBR to HBR data rates? - Why is there no video data stream output using the DisplayPort FPGA IP when downtraining from UHBR to HBR data rates? Description Due to a problem in the Quartus® Prime Pro Edition software version 25.1.1 and earlier, the DisplayPort FPGA IP core does not support downtraining from UHBR to HBR data rates. Hence, when a generic DP1.4 GPU initiates link training at DP2.0 rates and subsequently switches to HBR, no video data stream will be observed due to improper rate transition handling in the IP core. Resolution To work around this problem in the Quartus Prime Pro Edition software version 25.1.1 and earlier, please contact the Altera Support team to request a patch. This problem is fixed beginning with the Quartus Prime Pro Edition software version 25.3. Custom Fields values: ['novalue'] Troubleshooting 15017368154 False ['DisplayPort'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 25.3 25.1.1 ['Agilex™ 5 FPGAs and SoCs', 'Agilex™ 7 FPGAs and SoCs', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']