Warning (332049): Ignored create_generated_clock at .sdc: Option -phase: Invalid phase shift - Warning (332049): Ignored create_generated_clock at .sdc: Option -phase: Invalid phase shift Description Due to a problem in the Intel® Quartus® Prime Standard Edition software version 18.1 and earlier, you may see the warning message above in the fitter stage if you use the write_sdc -expand <project>.sdc command in the Intel® Timing Analyzer. This problem occurs if you have the Intel® Max® 10 soft LVDS Intel® FPGA IP in your design. Resolution To work around this problem, modify the create_generated_clock phase of <project>.sdc with the following: From -phase -90/1 modify to -phase [expr -90/1] This problem is fixed starting with the Intel® Quartus® Prime Standard Edition software version 19.1. Custom Fields values: ['novalue'] Troubleshooting 1507219225 False ['Soft LVDS IP'] ['FPGA Dev Tools Quartus® Prime Software Standard'] 19.1 18.1 ['MAX® 10 10 FPGAs'] ['novalue'] ['novalue'] ['novalue']