Why is the platform boot-up time delayed after configured with CVP periphery image when using R-tile PCIe non-x16 mode in Intel Agilex® 7 FPGAs? - Why is the platform boot-up time delayed after configured with CVP periphery image when using R-tile PCIe non-x16 mode in Intel Agilex® 7 FPGAs? Description Due to a problem in Intel® Quartus® Prime Pro Edition Software version 23.2 and earlier, you may observe longer platform boot-up time after configured with CVP periphery image when using R-tile for all PCIe mode (except x16 mode) in Intel Agilex® 7 FPGAs. The delay boot-up time may vary depending on port enumeration handling. The non-CVP port fails enumeration, but this issue is not impacting Configuration via Protocol (CVP) as port0 enumerated. Resolution To work around this problem, you can configure the FPGA with a CVP core image (.core.rbf). This problem is planned to be fixed in a future release of Intel® Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 15013718604 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 23.2 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']