Why do I see the link width down-configured to a lower link width occasionally during cold and warm reset? - Why do I see the link width down-configured to a lower link width occasionally during cold and warm reset? Description When you perform a cold or warm reset, you may see the link width down-configured after achieving the expected link width in the P-Tile Avalon® Streaming FPGA IP for PCI Express*. This problem only happens on certain server platforms where the PCIe Endpoint device implemented using P-Tile Avalon Streaming FPGA IP enters link training and then proceeds to Polling.Active LTSSM state way before the Root Complex enters link training mode. In other words, the Endpoint LTSSM enters Polling.Active for 24ms, and then enters Polling.Compliance as the Root Complex has not entered the link training mode or exited from electrical idle is a condition precedent to the link width down-configured problem. While the failing signature of this problem is the Endpoint LTSSM enters Polling.Active and stays for 24ms twice, along with the Root Complex staying in Polling.Configuration for 19ms. Resolution There is a workaround that the link width down-configured problem can be effectively prevented if the condition precedent described above can be removed, either by having both the PCIe Endpoint device and the Root Complex enter link training mode around the same time. Otherwise, issue a hot reset when the link width down-configured is detected to allow the link to recover at the desired width. Custom Fields values: ['novalue'] Troubleshooting 15017897467 False ['P-Tile Avalon-ST for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 22.3 ['Agilex™ 7 FPGA F-Series', 'Stratix® 10 DX FPGA'] ['novalue'] ['novalue'] ['novalue']