How should I connect the refclk and adjpllin ports in the PLL Intel® FPGA IP when using the dedicated cascade path? - How should I connect the refclk and adjpllin ports in the PLL Intel® FPGA IP when using the dedicated cascade path? Description There are two reference clock inputs ( refclk and adjpllin ) when the PLL Intel® FPGA IP is configured with the Cascade Downstream PLL option enabled. Resolution You need to connect the upstream " Cascade out " signal to the adjpllin input port and you can leave the refclk input unconnected. Custom Fields values: ['novalue'] Troubleshooting 2205753661 False ['Avalon ALTPLL'] ['FPGA Dev Tools Quartus II Software'] 13.0 12.1 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']