What can I do if the ALTGX_RECONFIG IP reconfig_busy signal is stuck high on Arria II, Cyclone IV, or Stratix IV transceiver devices? - What can I do if the ALTGX_RECONFIG IP reconfig_busy signal is stuck high on Arria II, Cyclone IV, or Stratix IV transceiver devices? Description If the transceiver ALTGX_RECONFIG IP reconfig_busy signal is stuck high on Arria® II, Cyclone® IV, or Stratix® IV transceiver devices, you can enable and assert the ALTGX_RECONFIG IP reconfig_reset signal. Resolution You can enable the reconfig_reset signal on the ALTGX_RECONFIG IP using the instructions below. Open the ALTGX_RECONFIG IP. Enable \'Channel reconfiguration\'. Enable "Use \'reconfig_reset\' " in the \'Channel and TX PLL reconfiguration\' page. Press \'Finish\' to generate the IP. Connect a synchronous reset signal to the reconfig_reset port. The following rules apply to the reconfig_reset signal: The reconfig_reset signal must be synchronous to the reconfig_clk clock. The reconfig_reset signal must be high when the device enters user mode. The reconfig_reset signal must be asserted for at least one reconfig_clk clock cycle. Related Articles Can I use REFCLK pin to generate reconfiguration clock (reconfig_clk) in Stratix IV GX/GT and Arria II GX devices? Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 9.0 ['Arria® II GZ FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA'] ['novalue'] ['novalue'] ['novalue']