Introduction to the Multirate Ethernet PHY FPGA IP - 32 Minutes This online course will instruct you in how to use Altera® Multirate Ethernet PHY FPGA IP to build a 1G/2.5G/5G/10G Ethernet application targeting FPGA transceiver devices using the Quartus® Prime Pro software. In this course, you will learn the features of the transceiver and the PHY IP, how to configure and connect the IP for your application and how generate design examples to accelerate your understanding and implementation.. Course Objectives At course completion, you will be able to: • Describe the features and functionality of the 1G/2.5G/5G/10G Multirate PHY IP • Connect the 1G/2.5G/5G/10G Multirate PHY IP to your MAC and application logic • Configure a custom 1G/2.5G/5G/10G Multirate PHY IP solution for your target FPGA • Generate a design example to demonstrate Multirate PHY IP in complete solution Skills Required • Familiarity with common high-speed transceiver architecture OR viewing the appropriate "Transceiver Basics" training for your targeted device • Familiarity with FPGA/CPLD design flow • Familiarity with the Intel Quartus Prime Pro design software • Some familiarity with Platform Designer system building tool If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_O10GPHY. FPGA_O10GPHY. <p id="isPasted">Introduction to the Multirate Ethernet PHY FPGA IP</p>