Why does Mentor* ModelSim* simulation of the eSRAM Intel® FPGA IP generate X in the waveform? - Why does Mentor* ModelSim* simulation of the eSRAM Intel® FPGA IP generate X in the waveform?
Description In the Modelsim* SE 2020 version software, you may see 'X' in the simulation of the eSRAM Intel® FPGA IP due to an encrypted code problem in the simulator. Resolution To work around this problem, run the simulation with the prior Modelsim* SE 2020 (e.g., Modelsim SE 2019.2) version. This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.3.
Custom Fields values:
['novalue']
Troubleshooting
14011174455
True
['eSRAM IP']
['FPGA Dev Tools Quartus® Prime Software Pro']
21.3
20.3
['Agilex™ 7 FPGAs and SoCs']
['novalue']
['novalue']
['novalue'] - 2022-12-12
external_document