40-100GbE IP Core Might Provide Incorrect Parity Error Information in MAC_HW_ERR Register Bit 5 - 40-100GbE IP Core Might Provide Incorrect Parity Error Information in MAC_HW_ERR Register Bit 5 Description The MAC_HW_ERR register (offset 0x120) field in bit 5 should indicate the presence or absence of a parity error in the DOE command FIFO buffer section. However, this bit might have an incorrect value. Resolution This issue has no workaround. Ensure you do not rely on the value in bit 5 of the MAC_HW_ERR register in versions 15.0 and earlier of the 40-100GbE IP core. This issue is fixed in version 15.1 of the 40-100GbE IP core. Custom Fields values: ['novalue'] Troubleshooting FB328938; True ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 15.1 14.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']