Do I have to connect VREF pin of the I/O bank where mem_clk pins are located when implementing ALTMEMPHY based IP in Arria II GX devices? - Do I have to connect VREF pin of the I/O bank where mem_clk pins are located when implementing ALTMEMPHY based IP in Arria II GX devices? Description Yes, you have to connect VREF pin of the I/O bank where mem_clk pins are located to either 0.75V/0.9V when implementing ALTMEMPHY based DDR3/DDR2 SDRAM IP in Arria® II GX devices. Although the input buffer of the differential SSTL standard in Arria II GX device is true differential and VREF pin is not needed, the mimic input feedback path(mem_clk only) is using single ended buffer. Hence, you need to ensure the VREF pin of the I/O bank where the mem_clk pins are located is powered up to 0.75V/0.9V for DDR3/DDR2 SDRAM interface respectively. Related Articles Do differential SSTL and HSTL inputs in Cyclone III and Cyclone IV series devices require a VREF input to reference? Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 11.1.2 ['Arria® II GX FPGA'] ['novalue'] ['novalue'] ['novalue']