Why does a compilation error happen when using the IOPLL in the HVIO bank in place of a GTS System PLL for the PMA/FEC Direct PHY IP and all other protocol IPs for the Agilex™ 3 FPGA and Agilex™ 5 FPGA designs? - Why does a compilation error happen when using the IOPLL in the HVIO bank in place of a GTS System PLL for the PMA/FEC Direct PHY IP and all other protocol IPs for the Agilex™ 3 FPGA and Agilex™ 5 FPGA designs? Description Due to a problem in the Quartus® Prime Pro Edition software version 25.1 and earlier, you may see a compilation error when using the IOPLL in the HVIO bank in place of a GTS System PLL for the PMA/FEC Direct PHY IP and all other protocol IPs for the Agilex™ 3 FPGA and Agilex™ 5 FPGA designs. The error message and critical warning below are displayed “ ERROR: Argument <node_object> is an object filter that matches no objects. Specify one matches only one object. ” “ Read_sdc failed due to errors in the SDC file ”. Resolution There is no workaround currently for this problem. The System PLL must be used for the IPs requiring it. This means that for single GTS Transceiver bank devices, PCIe* and non-PCIe protocols cannot be used together in a design. This problem will be fixed in a future release of the Quartus® Prime Pro Edition software. Custom Fields values: ['novalue'] Errata 15015212590 False ['IOPLL IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 24.1 ['Agilex™ 5 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']