Why does “Override MPU Clocks” fail to work in Hard Processor System Agilex™ 5 FPGA IP? - Why does “Override MPU Clocks” fail to work in Hard Processor System Agilex™ 5 FPGA IP? Description The Hard Processor Agilex™ 5 FPGA IP reports the following error when selecting “Override MPU Clocks”. Error: divide by zero while executing "expr ($Fref / $count)" (procedure "pll_compute_clock_counter" line 5) invoked from within "pll_compute_clock_counter $mpu_ref $mpu_freq dsu_ctr" (procedure "clkmgr::calculate_clk_mgr_values" line 151) invoked from within "clkmgr::calculate_clk_mgr_values" (procedure "validate" line 9) invoked from within "validate" This problem is due to incorrect calculation for valid clock configuration. Resolution Warnings and errors are added in the Quartus ® Prime Pro Edition Software version 24.2 and later to report unsupported clock configurations and to include suggestions for correct configurations. Custom Fields values: ['novalue'] Troubleshooting 14022025744,15015964073,15015973820,18037868602 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.2 24.1 ['Agilex™ 5 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']