Invalid Binary for FPGA Stratix 10 Nodes - Invalid Binary for FPGA Stratix 10 Nodes I recently built new FPGA images for the DPC++ code I have using the new 2021.3 version of the tools. I had previously built the same source code using the 2021.1 version of the tools and executed the designs on Stratix 10 nodes. I noticed that there are new "fast-math" optimizations for FPGAs with the new version of the tools, so I wanted to investigate the changes. The compile/synthesis completes successfully, generates all reports, and provides the executable images. When connected to a node with a Stratix 10 device, I run the executable and get the error: terminate called after throwing an instance of 'cl::sycl::runtime_error' what(): Native API failed. Native API returns: -42 (CL_INVALID_BINARY) -42 (CL_INVALID_BINARY) Aborted Is there a disconnect between the compile nodes and the runtime nodes in terms of versioning? I am also wondering if Stratix now requires PACsign like the Arria nodes require too. Either way, there's some disconnect and I cannot find information on what changed. For reference, the command I use to compile is: dpcpp -I $INTELFPGAOCLSDKROOT/include/ref -qactypes -fintelfpga -Xshardware -Xsboard=intel_s10sx_pac:pac_s10 source.cpp helper.cpp -Xsclock=400MHz -Xsprofile -v -o fpga.hw Replies: Re: Invalid Binary for FPGA Stratix 10 Nodes I apologize this was more DevCloud specific than HLS. Solution found at: community.intel.com/t5/Intel-DevCloud/Invalid-Binary-for-FPGA-Stratix-10-Nodes/m-p/1300748#M2604 Replies: Re: Invalid Binary for FPGA Stratix 10 Nodes Investigating this issue further, I am seeing the same error when trying to execute an example vector add program. Is this something to do with changes to USM? Command to compile: dpcpp -I $INTELFPGAOCLSDKROOT/include/ref -qactypes -fintelfpga -Xshardware -Xsboard=intel_s10sx_pac:pac_s10 vecadd.cpp -Xsclock=400MHz -Xsprofile -v -o fpga.hw Attached is the source code from dpc++FPGA direct programming examples (vecadd.cpp). Compiled on "nodes=1:fpga_compile:ppn=2" node, executed fpga.hw on "nodes=1:stratix10:ppn=2" node. Passes CPU and FPGA emulation. Full output: Running on device: pac_s10_usm : Intel PAC Platform (pac_ee00000) Caught a SYCL host exception: Native API failed. Native API returns: -42 (CL_INVALID_BINARY) -42 (CL_INVALID_BINARY) terminate called after throwing an instance of 'cl::sycl::runtime_error' what(): Native API failed. Native API returns: -42 (CL_INVALID_BINARY) -42 (CL_INVALID_BINARY) Aborted