How should the CKE signal be terminated for DDR3 and DDR4 interfaces? - How should the CKE signal be terminated for DDR3 and DDR4 interfaces? Description The CKE signal is pulled down to GND on the DDR3 HiLo daughter card and terminated with a Thevenin parallel termination on the DDR4 HiLo daughter card. Resolution All address and command signals, including the CKE signal, should use a fly-by termination for Arria®10 and Stratix®10 DDR3 and DDR4 interfaces. These signals should be terminated with a resistor to VTT at the end of the fly-by topology. This termination is required only for discrete memory device implementations and is not required for DIMMs. Custom Fields values: ['novalue'] Troubleshooting FB: 477716; False ['External Memory Interfaces Arria® 10 FPGA IP', 'External Memory Interfaces Stratix® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software'] novalue 17.0 ['Arria® 10 FPGAs and SoCs', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']