Error(13149): EMIF/PHYLite systems sharing a PLL reference clock do not have identical reset inputs for following io_aux atoms - Error(13149): EMIF/PHYLite systems sharing a PLL reference clock do not have identical reset inputs for following io_aux atoms Description When you implement an Intel® Arria® 10 External Memory Interfaces IP and an Intel Arria 10 PHYLite IP sharing the PLL reference clock and reset in the same I/O column, you may see this fitter error. Resolution To work around this problem, tie the Intel® Arria® 10 PHYLite IP reset port to "1". Custom Fields values: ['novalue'] Troubleshooting FB: 2205700453; False ['PHY Lite for Parallel Interfaces Stratix® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 18.1.1 ['Arria® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue'] - 2023-01-16