Why does Agilex™ 7 R-Tile Compute Express Link* (CXL) 1.1/2.0 FPGA IP not support burst operation on CXL.io Avalon® Memory Mapped Interface? - Why does Agilex™ 7 R-Tile Compute Express Link* (CXL) 1.1/2.0 FPGA IP not support burst operation on CXL.io Avalon® Memory Mapped Interface? Description Due to a problem in Quartus® Prime Pro Edition Software version 23.3 and earlier, the Agilex™ 7 R-Tile Compute Express Link* (CXL) 1.1/2.0 FPGA IP doesn't support burst operation on the Avalon® Memory Mapped Interface of the CXL.io channel. Resolution This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 15012695561 False ['R-Tile for Compute Express Link Solution'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 22.4 ['Agilex™ 7 FPGA I-Series'] ['novalue'] ['novalue'] ['novalue']