# ** Error (suppressible): (vsim-10000) <simulation directory>/sim/<IP name>.v(61): Unresolved defparam reference to 'scfifo_component' in scfifo_component.add_ram_output_register. - # ** Error (suppressible): (vsim-10000) <simulation directory>/sim/<IP name>.v(61): Unresolved defparam reference to 'scfifo_component' in scfifo_component.add_ram_output_register. Description Due to a problem in the Quartus® Prime Standard Edition Software version 18.1 and earlier, you may see this error message if you run the nativelink simulation in the Modelsim simulator. This is because you have a FIFO IP in your design, and this IP does not support VHDL simulation. Resolution To work around this problem, change the format for the output netlist from VHDL to Verilog HDL in: Assignment -> Settings -> Eda Tools Settings-> Simulation -> Format for output netlist before you run the native link simulation. Custom Fields values: ['novalue'] Troubleshooting 1507074337 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Standard'] novalue 18.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']