Why does the PCI Express Hard IP core not transition through all the required hot reset LTSSM states in the simulation? - Why does the PCI Express Hard IP core not transition through all the required hot reset LTSSM states in the simulation? Description Due to a problem in the soft reset controller, when hot reset is applied, the LTSSM does not go through every state expected when initiating hot resets. Resolution This problem can be fixed with the following soft logic code in the file altpcie_rs_serdes.v near line 526: exits_r <= ((rx_signaldetect == 8\'b00000000) & (dl_ltssm_r == 5\'h14)) | (l2_exit_r == 1\'b0) | (hotrst_exit_r == 1\'b0) | (dlup_exit_r == 1\'b0) | (dl_ltssm_r == 5\'h10) /*| (dl_ltssm_r == 5\'h14)*/ | (recovery_rst == 1\'b1) | (ext_dect_quiet==1\'b1); This problem is fixed in Intel® Quartus® Software Version 14.0 Custom Fields values: ['novalue'] Troubleshooting 2205756052 False ['Simulation'] ['FPGA Dev Tools Quartus II Software'] 14.0 11.1 ['Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']