Why do the signals tx_ex_delay_valid and rx_delay_valid of the CPRI Intel® FPGA IP core not read to clear as expected? - Why do the signals tx_ex_delay_valid and rx_delay_valid of the CPRI Intel® FPGA IP core not read to clear as expected? Description Due to a problem in the CPRI Intel® FPGA IP core version 21.2 and earlier, you might see that the tx_ex_delay_valid and rx_ex_delay_valid operate as read only signals and do not read to clear as descripted in the CPRI Intel® FPGA IP Core User Guide. Resolution This problem is fixed starting with the Intel® Quartus® Prime Pro/Standard Edition Software version 21.3. Custom Fields values: ['novalue'] Troubleshooting 15010086723 False ['Interfaces Communications CPRI (Primary)'] ['novalue'] novalue novalue ['Agilex™ 7 FPGAs and SoCs', 'Arria® 10 FPGAs and SoCs', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']