Arria® V GT FPGA Overview - Arria® V GX and GT FPGAs offer the lowest total power for mid-range applications by using the 28 nm low power process. Product Pages Broadcast Test Wireline Overview Arria V GX and GT FPGA offers the lowest total power for mid-range applications by using the 28 nm low power process to deliver the lowest static power, offering the lowest power transceivers for speeds up to 10.3125 Gbps, and providing superior fabric with hard IP designed to lower dynamic power. Arria V GT FPGA Product Table Benefits Features enhanced transceiver capabilities for high-speed serial interfaces, supporting applications such as wireless base stations, test equipment, and wireline communications that require reliable, high-bandwidth connectivity. Enhanced High-Speed Transceiver Support Offers signal integrity features and flexible clocking resources that simplify design challenges in systems operating across multiple serial standards. Simplified Multi-Standard Interface Design Maintains low power operation while enabling system designers to address advanced communication protocol requirements in space-constrained environments. Low-Power Communication Solutions Key Features Provides robust high-speed serial interfaces for communications and wireless infrastructure systems requiring reliable, high-bandwidth connectivity. Enhanced High-Speed Transceivers Includes flexible clocking and jitter management to streamline design across multiple serial standards. Simplified Multi-Standard Interface Design Supports high-speed communication while maintaining low power consumption for energy-sensitive system designs. Low-Power Operation Applications Wireline Industrial Security IP, Example Designs & Software Get Started: IP, Example Designs and Software IP 10GBASE-R PHY FPGA IP The 10GBASE-R PHY FPGA Intellectual Property (IP) core can be used with either Altera FPGA IP for 10G Ethernet MAC or with a customer-developed Ethernet MAC via a standard XGMII interface running at 156.25 Mbps. Nios V Processors By leveraging the RISC-V instruction set architecture (ISA), the Nios V processors offer scalable solutions that enable a spectrum of applications ranging from simple embedded systems to complex, high-performance applications. Example Designs FPGA Developer Site GitHub site that provides a single location for developers to find and use Altera example designs, software, drivers, and associated collateral. Example Design Store This site offers essential FPGA developer resources—including example designs, documentation, and software tools—to accelerate your design process and reduce time to production. Software Quartus® Prime Standard Edition Design Software Documentation Documents Documentation Arria V GT Device Overview Arria V Product Table Arria V Datasheet Support Resources Arria® V GT FPGA