How do I stitch multiple MIF files generated by the Quartus II software into a single MIF file, for fPLL reconfiguration in Stratix V, Arria V and Cyclone V devices? - How do I stitch multiple MIF files generated by the Quartus II software into a single MIF file, for fPLL reconfiguration in Stratix V, Arria V and Cyclone V devices? Description You can stitch multiple Memory Initialization Files (MIF) generated by Quartus® II software into a single MIF file for fPLL reconfiguration in Stratix® V, Arria® V and Cyclone® V devices using the script provided in the link below: merge_mif.tcl To use the script, follow the steps below: 1. Place the tcl file and the MIF files in the same folder. 2. Source the merge_mif.tcl in tcl console. 3. Type the following command to stich 2 mif files (e.g A.mif and B.mif) into output.mif. Command : stitch A.mif B.mif [output.mif] Note : If you do not specify the optional [output.mif] paramater, it defaults to merged.mif. 4. In merged.mif, the content of B.mif comes after A.mif. 5. Repeat step 3 if you want to merge another MIF file (e.g C.mif) to merged.mif . You can stitch multiple MIF files together as long as the depth of the merged file does not exceed 512. Refer to AN661 : Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig Megafunctions (PDF) for more information on performing PLL reconfiguration via MIF streaming. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® V FPGAs and SoCs', 'Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V FPGAs and SoCs', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Stratix® V E FPGA', 'Stratix® V FPGAs', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']