Why does my F-Tile Ethernet Intel® FPGA Hard IP Design Example fail to acquire corrected received data in 50GE-2 OTN Variant ? - Why does my F-Tile Ethernet Intel® FPGA Hard IP Design Example fail to acquire corrected received data in 50GE-2 OTN Variant ? Description Due to a problem in the F-Tile Ethernet Intel® FPGA Hard IP in the Intel® Quartus® Prime Software v21.2, RX PCS66 output data is corrupted in 50GE-2 OTN variant (both FGT and FHT transceivers) Resolution This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.3. Custom Fields values: ['novalue'] Troubleshooting 16013290631 True ['Ethernet'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 21.3 21.2 ['Agilex™ 7 FPGA I-Series'] ['novalue'] ['novalue'] ['novalue']