Why does my Stratix® 10 device L-Tile or H-Tile transceiver PHY RTL simulation hang in the reset state? - Why does my Stratix® 10 device L-Tile or H-Tile transceiver PHY RTL simulation hang in the reset state? Description Your Stratix® 10 device L-Tile or H-Tile transceiver PHY RTL simulation may hang in the reset state if you have not applied a Power On Reset (POR) pulse to the reconfig_reset signal of the Avalon Memory Mapped (AVMM) reconfiguration interface. Resolution To work around this problem, you can apply a two reconfig_clk cycle pulse to the reconfig_reset signal at the start of your RTL simulation. Custom Fields values: ['novalue'] Troubleshooting FB: 571131; False ['L-Tile H-Tile Transceiver Native PHY Stratix® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 18.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']