Why doesn't the Platform Designer (Standard) Component Editor add all of my signals? - Why doesn't the Platform Designer (Standard) Component Editor add all of my signals? Description In the Platform Designer (Standard) Component Editor, you may see that not all inputs and outputs have been added after running Analyse Synthesis Files . This occurs when the IO are VHDL types such as bit, std_ulogic or custom types Resolution To work around this limitation, either add the ports manually to your component or use std_logic type IO. Custom Fields values: ['novalue'] Troubleshooting FB: 538759; False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Standard'] 18.0 17.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']