Designing with Agilex® 3 & Agilex® 5 SoC FPGAs - 5 Days - Enroll Now This 5-days deep training provides all the necessary know-how for hardware engineers that would like to design with the Altera® Agilex® 3 or Agilex® 5 SoC FPGA family. The training provides extensive hands-on labs to experience with the various features. The training starts by introducing the Agilex 3 & Agilex 5 SoC families and their architecture. Then the Hyperflex™ architecture and how to use it efficiently is discussed in details. The Quartus® Prime Pro advanced features that support Agilex 3 & Agilex 5 are introduced along with practical hands-on labs. In the second day the training continuous with the high-speed memory interfaces, high speed serial interfaces (GTS transceivers and various IPs), and the MIPI interface with CSI2/DSI2. In the third day the Hardware Processor System (HPS) is introduced along with its peripherals, interfaces, Network on Chip (NoC), and Arm Cortex-A55 & Arm Cortex-A76 architecture and capabilities. This part covers also the boot flow in details, and how to generate the first and second bootloaders (FSBL, SSBL). In the fourth day the Agilex 3 & Agilex 5 configuration schemes are discussed in details including the Remote System Update (RSU) design flow. In addition, the Agilex 3 & Agilex 5 security features are discussed in details including the Secure Device Manager (SDM) and the secure boot flow. In the fifth day the Agilex 3 & Agilex 5 DSP with Tensor block architecture is introduced. Then the deployment of AI IP design flow is discussed in details. Course Content : 1. Introduction to Agilex 3 & Agilex 5 FPGAs 2. Hyperflex Architecture 3. Quartus Prime Pro Design Software for Agilex 3 & Agilex 5 4. High-Speed Memory Interfaces in Agilex 3 & Agilex 5 5. Implementing High-Speed Interfaces in Agilex 3 & Agilex 5 6. Implementing Ethernet & TSN in Agilex 3 & Agilex 5 7. Video Solutions with Agilex 3 & Agilex 5 8. Agilex 3 & Agilex 5 Hard Processor System Deep Dive 9. Agilex 3 & Agilex 5 Configuration Schemes 10. Agilex 3 & Agilex 5 Remote System Update 11. Agilex 3 & Agilex 5 Security & Safety Features 12. Agilex 3 & Agilex 5 Enhanced DSP with AI Tensor Block 13. Deploy AI IP Design Flow in Agilex 3 & Agilex 5 FPGAs Prerequisites: - FPGA design - Quartus® Prime Pro software - Platform Designer Tool Tools Required: - Quartus Prime Pro software - Questa. HONT_DAG3AG5.