Timing violation in ls_clk[0] clock domain of HDMI RX core IP - Timing violation in ls_clk[0] clock domain of HDMI RX core IP Description HDMI RX core IP may encounter timing violation if ls_clk[2:0] is clocked from 3 separate clock source instead of single clock source. This is due to improper handling of clock domain crossing of individual TMDS data path to ls_clk[0] clock domain in HDMI RX core IP. Resolution Drive all the 3 ls_clk[2:0] from the same clock source and performing data synchronization to that single clock source prior to connecting to HDMI RX core IP. User may also refer to Arria® 10 HDMI design example mr_hdmi_rx_core_top.v design file for the demonstration of the connection. Example design can be generated from HDMI core IP. This issue is fixed in Quartus® Prime version 17.0 update 1. Custom Fields values: ['novalue'] Troubleshooting FB: 462426; True ['HDMI'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 17.0.1 17.0 ['Arria® V FPGAs and SoCs', 'Cyclone® V FPGAs and SoCs', 'Arria® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']