Which HPS SDRAM Controller command ports are associated with which AXI interfaces? - Which HPS SDRAM Controller command ports are associated with which AXI interfaces? Description The Cyclone® V and Arria® V HPS SDRAM controller allows up to 3 AXI™ interfaces. The following shows the mapping of the SDRAM controller command port to the AXI interface read/write channel. • Command port 0: f2h_sdram0 AXI Read commands • Command port 1: f2h_sdram0 AXI Write commands • Command port 2: f2h_sdram1 AXI Read commands • Command port 3: f2h_sdram1 AXI Write commands • Command port 4: f2h_sdram2 AXI Read commands • Command port 5: f2h_sdram2 AXI Write commands Resolution This information is included starting with release 15.1 of the Arria® V and Cyclone® V Handbook. Custom Fields values: ['novalue'] Troubleshooting n/a False ['novalue'] ['FPGA Dev Tools Quartus II Software'] 15.1 13.0 ['Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']