Why does the Fitter report under the GXB Receiver Channel show the incorrect input clock frequency for the IP Compiler for PCI Express in Qsys? - Why does the Fitter report under the GXB Receiver Channel show the incorrect input clock frequency for the IP Compiler for PCI Express in Qsys? Description Due to a problem in the Quartus II software version 11.1 and later, PCIe IP generated in Qsys may show the input clock frequency as 100 MHz even though you have selected 125 MHz in the 'reference clock frequency' field. Resolution To work around this problem. follow the steps below: Open the Qsys-generated *altgx_internal*.v file in a text editor and delete the following line: // Retrieval info: PRIVATE: LOCKDOWN_EXCL STRING "PCIE". Open the *altgx_internal* megafunction using the MegaWizard™ Plug-in Manager Change the input frequency to 125 MHz, then click Finish. Recompile your design in the Quartus II software. This problem is scheduled to be fixed in a future release of the Quartus II software. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 11.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']