Cyclone V HMC IBIS Model - Cyclone V HMC IBIS Model I cannot find the IBIS model for the Cyclone V HMC (Hard memory controller). I tried looking here https://www.intel.com/content/www/us/en/support/programmable/support-resources/board-layout/ibs-ibis-index.html but these models appear to only contain the general purpose FPGA fabric I/O models. Where can I find the HPS DDR IBIS file? Replies: Re: Cyclone V HMC IBIS Model This is what I had ended up using. Thank you. Replies: Re: Cyclone V HMC IBIS Model Hi John_C, Do you have any further questions or feedback in this forum? Regards, Adzim Replies: Re: Cyclone V HMC IBIS Model Hi John_C, I think you should follow the IO standard that the IP is currently using to connect the memory component. For example DDR3, the IO standard is SSTL-15. You can use SSTL15_<io>_<feature> or similar IBIS model. Regards, Adzim