Why does the TX Throughput value shown in Ethernet Toolkit for the F‑Tile Ethernet FPGA Hard IP Design Example not match the expected data rate? - Why does the TX Throughput value shown in Ethernet Toolkit for the F‑Tile Ethernet FPGA Hard IP Design Example not match the expected data rate? Description In F‑Tile Ethernet FPGA Hard IP Design Example generated using Quartus® Prime Pro Edition software versions 25.3.1 and earlier , you may notice that the TX Throughput reported by the Ethernet Toolkit appears lower than the expected line rate. This behavior is expected. The ROM‑based packet generator included in the design example has the following characteristics: It defaults to a 64‑byte packet size, and It inserts non‑zero inter‑packet gaps (IPG) These factors inherently reduce the measured throughput compared to the theoretical maximum line rate. Resolution To accurately validate the TX Throughput of the design, Altera recommends to use a standard Ethernet traffic tester capable of running in client loopback mode. This allows to measure the actual TX throughput without limitations imposed by the built‑in ROM packet generator. There is no plan to fix this problem. Custom Fields values: ['novalue'] How To 15018821947 novalue ['Interfaces Ethernet'] ['FPGA Dev Tools Quartus® Prime Software Pro', 'FPGA Dev Tools Quartus® Prime Software Standard'] novalue 24.2 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']