Partial Reconfiguration for Altera® FPGAs: Design Guidelines & Host Requirements - 36 Minutes This training is part 2 of 4. The Partial Reconfiguration (PR) feature found in Altera® FPGA devices allows you to, at any time during normal operation, replace functional parts of your design with completely different logic while the rest of your design continues to operate normally. Combined with transceiver and PLL dynamic reconfiguration, and you have a complete solution for runtime functionality changes and design upgrades. This part of the training discusses the guidelines for creating a PR design, including the creation of a port superset and freeze logic. It also discusses the requirements for a PR host, the logic added to the design's static region or an external device to control PR operations. Course Objectives At course completion, you will be able to: Get an introduction to the Partial Reconfiguration (PR) feature and its many uses Understand the Basic design flow and Guidelines for creating a PR design Add the PR Controller IP and other PR IP to the design to simplify the creation of a PR host compile the design and use the generated programming files to perform PR Skills Required Basic knowledge of the Altera® Quartus Prime software knowledge of creating FPGA designs in a hardware description language (Verilog or VHDL) If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OPR201. FPGA_OPR201. <p>Partial Reconfiguration for Altera FPGA Devices: Design Guidelines & Host Requirements</p>