Why does the Quartus® Prime Pro Software allow multiple F-Tile Reference and System PLL Clocks IP to be instantiated per F-Tile in my design? - Why does the Quartus® Prime Pro Software allow multiple F-Tile Reference and System PLL Clocks IP to be instantiated per F-Tile in my design? Description Due to a problem in the Quartus® Prime Pro Edition Software Version 24.3 and earlier, multiple F-Tile Reference and System PLL Clocks IP are incorrectly allowed to be instantiated per F-Tile. Creating multiple instances of this IP in your F-Tile design will cause the System PLL reference clock, FGT reference clock monitor, and protection circuitry to be non-functional. Resolution To work around this problem in the Quartus® Prime Pro Edition Software Version 24.3 and earlier, ensure that only one instance of the F-Tile Reference and System PLL Clocks IP is instantiated per F-Tile. This problem has been fixed starting in version 24.3.1 of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 14023640915 False ['F-Tile Reference and System PLL Clocks IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.3.1 24.3 ['Agilex™ 7 FPGAs and SoCs', 'Agilex™ 9 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']