MCDMA/PCIe - what is frequency of coreclkout_hip? - MCDMA/PCIe - what is frequency of coreclkout_hip? Hello, In the user guide, with H-tile types - Gen3x8, application clock or coreclkout_hip frequency = 250 MHz. But I could not verify it in the TA clock report. Instead, I could see "dut|dut|hip|altera_pcie_s10_hip_ast_pipen1b_inst|altera_pcie_s10_hip_ast_pllnphy_inst|g_phy_g3x8.phy_g3x8|phy_g3x8|xcvr_hip_native|ch0" and its frequency is 500 MHz. It matches the constraints below: set clk_source_freq "250.0 MHz" set datarate_100m 80 ... # 500M for aibx2 clocks if BW less or equal 64G } elseif { [expr $datarate_100m * 8] <= 640 } { dict set multiply_factor_dict aib_internal_div 2 dict set divide_factor_dict aib_internal_div 1 dict set multiply_factor_dict clkout 1 dict set divide_factor_dict clkout 1 } ... create_generated_clock \ -name $inst|xcvr_hip_native|ch${channels} \ -source $no_inst_tx_internal_div_reg \ -master_clock $tx_internal_div_reg_name \ -multiply_by [dict get $multiply_factor_dict clkout] \ -divide_by [dict get $divide_factor_dict clkout] \ $no_inst_tx_clkout -add I think this clock is transport-layer clock and it is used to derive application clock/ coreclkout_hip / pld_clk250 as in the code below assign coreclkout_hip = enable_512adapter_hwtcl? pld_clk250 : coreclkout_hip_wire ; ... altera_ep_g3x16_avst512_io_pll_s10 altera_avst512_iopll ( .outclk_0 (pld_clk250), .refclk (coreclkout_hip_wire), .rst (~pin_perst), .locked (iopll_locked), .permit_cal (serdes_pll_locked_wire) ); Do I understand it correctly? If it is correct, then, it is confusing to me. Here is what I found. I use application clock / coreclkout_hip as the refclk of PLL to derive another clock domain (200 MHz). The setting of PLL is Reference clock = 250 MHz Output clock = 200 MHz However, when re-check the TA clock report: Reference clock = 500 MHz Output clock = 400 MHz what is wrong here? My platform is Stratix 10 MX | Quartus Prime Pro ver 22.2 Thank you, TN Replies: Re: MCDMA/PCIe - what is frequency of coreclkout_hip? Hi, Thanks for your confirmation. That clears my doubt. That means '''coreclkout_hip' is not 250MHz as specified in the user guide. Regards, TN Replies: Re: MCDMA/PCIe - what is frequency of coreclkout_hip? Hi, My answer should be yes for your question. Regards, Wincent_Intel Replies: Re: MCDMA/PCIe - what is frequency of coreclkout_hip? Hi Wincent, Sorry for my late reply due to holiday. From your attached snippet, one thing can be confirmed is MCDMA clock is 250 MHz. Your statement: @Wincent_Altera wrote: The paths shown in the timing report are the QHIP paths and not inside MCDMA. And because the reference clock of PLL is taken from "coreclkout_hip". It means the reference clock is QHIP paths and it is not 250 MHz, isn't it? Regards, TN Replies: Re: MCDMA/PCIe - what is frequency of coreclkout_hip? Hi, The input clock frequency of H-Tile MCDMA(intel_pcie_mcdma) is 250 MHz and the IP runs on 250MHz only. Please refer the attached snippet. The paths shown in the timing report are the QHIP paths and not inside MCDMA. Time period = 4ns. Clock Frequency( dut.dut.mcdma.clk) = 250 MHz. Replies: Re: MCDMA/PCIe - what is frequency of coreclkout_hip? Hi, Thanks for your understanding. I just close in my support portal. This thread still remain for public command, I will keep you in post if there is any update related team. If you have a new question, feel free to open a new thread to get support from Intel experts. If you feel your support experience was less than a 9 or 10, please allow me to correct it before closing or let me know the cause so that I may improve your future support experience. Regards, Wincent_Intel Replies: Re: MCDMA/PCIe - what is frequency of coreclkout_hip? Hi Wincent, Thanks for the confirmation and your support. I think you can close the case now. Regards, TN Replies: Re: MCDMA/PCIe - what is frequency of coreclkout_hip? Hi, Apologize for late reply, as I am looking at the design provided by you. I am able to replicate your issue based on the MCDMA design provided in the IP catalog of H-tile. I am getting the same result as yours which is 500MHz. The next action I will do is to raise an internal ticket to the responsible team. Temporarily we do not have any solution to this issue, expected to be fixed in next release version of Quartus. I will update you if there is any update from the related team. Regards, Wincent_Intel Replies: Re: MCDMA/PCIe - what is frequency of coreclkout_hip? Hi, Sure, this is the design I mentioned. My Quartus version is 22.2 Regards, TN Replies: Re: MCDMA/PCIe - what is frequency of coreclkout_hip? Hi, Can you share the .qar file with me ? So that I can help to look at ur design. Regards, Wincent_Intel Replies: Re: MCDMA/PCIe - what is frequency of coreclkout_hip? Hi, There are no timing issues (setup or hold time violation yet) I made a simple system that is MCDMA => DC-FIFO => DC-FIFO => MCDMA I observed the same behavior @output clock of PLL. That means "coreclkout_hip" frequency should be 500 MHz. Could you please suggest which sub-forum should I post the question regarding this? Regards, TN Replies: Re: MCDMA/PCIe - what is frequency of coreclkout_hip? Hi Wincent, No problem. My mistake ... the statement might not be clear. Here is the scenario: The ratio of PLL 250MHz/200MHz" - I expected input clk = 250 MHz and output clock = 200 MHz However, I observed the actual frequency of PLL output clk is 400 MHz => Hence, my implication is the input frequency is 500 MHz which means coreclkout_hip = 500 MHz instead of 250MHz as stated in the user guide. --- The output clock which is fed to a DC-FIFO also results the same frequency. Regards, TN Replies: Re: MCDMA/PCIe - what is frequency of coreclkout_hip? Hi, There is some reason the frequency is double. I suggest you to check the RTL design and see what is connected to the output. I am not an expert in timing issues, As I am supporting PCIe design in most of the time. Another suggestion to get better support is open a new case with title and category related to timing. So that the correct expert will be assigned to help you. Do attach the .qar and timing report for that. Regards, Wincent_Intel Replies: Re: MCDMA/PCIe - what is frequency of coreclkout_hip? Hi, Apologize for late reply due to holiday. Based on the user guide, the maximum H-tile types - Gen3x8, application clock is 250 MHz. I dont understand your statement as "With the setup ratio 250MHz/200MHz, it expects "coreclkout_hip" should be 500 MHz instead of 250 MHz." Can you please clarified more on this ? by logic when you set it as 250 why it shall get 500 MHz instead of 250Mhz ? Regards, Wincent_Intel Replies: Re: MCDMA/PCIe - what is frequency of coreclkout_hip? Hi, Here is the screenshot of clock report The clk_wizard_clk_user is output_clk of PLL. And, this is my PLL setting Thanks and Regards, TN Replies: Re: MCDMA/PCIe - what is frequency of coreclkout_hip? Hi, the printscreen is not clear, could you please provide again ? so that I can confirm the issue ? Regards, Wincent_Intel Replies: Re: MCDMA/PCIe - what is frequency of coreclkout_hip? Hi, Thanks for your reply. Could you please make this case open? After @FvM reply, I have checked the actual frequency of PLL output_clk = 400 MHz. With the setup ratio 250MHz/200MHz, it expects "coreclkout_hip" should be 500 MHz instead of 250 MHz. Therefore, I still need to discuss more to know what I was wrong. Thanks and Regards, TN Replies: Re: MCDMA/PCIe - what is frequency of coreclkout_hip? Hi, Glad that you get your answer. So do you still have any further questions on this forum case ? Or everything is nice ? if yes, I shall close this case from my place and leave this thread to the public community. Regards, Wincent_Intel Replies: Re: MCDMA/PCIe - what is frequency of coreclkout_hip? Hi, Thanks for your reply! That is why I was confused. Under "Clock" report in Timing Analysis, it showed 'output_clk" of PLL is 400 MHz. Meanwhile, my setting ratio of PLL is 'refclk/output_clk' = 250MHz/ 200MHz That's why I thought refclk frequency should be: 500 MHz, and it violates the user guide where the frequency should be 250 MHz. Thanks and Regards, TN Replies: Re: MCDMA/PCIe - what is frequency of coreclkout_hip? Would expect to see actual PLL frequencies in timing analysis report under "clocks" and also in synthesis report under Resources/PLLs. Replies: Re: MCDMA/PCIe - what is frequency of coreclkout_hip? Hi, Thanks for your help. That means: In this case, we could not see the actual clock frequency in the Timing Analysis report, and the only way to know the exact number is by reviewing the code. Is that correct? Thanks and Regards, TN Replies: Re: MCDMA/PCIe - what is frequency of coreclkout_hip? Hi, The way you review the clock frequency at the first post shall be correct as per mention in the user guide. Regards, Wincent_Intel Replies: Re: MCDMA/PCIe - what is frequency of coreclkout_hip? Hi, Thanks for your clarification. So, how could I review the actual clock frequency? Regards, TN Replies: Re: MCDMA/PCIe - what is frequency of coreclkout_hip? Hi, I think that indicates the Clock Fmax. If you changed the optimization Mode from Balanced to Aggressive Area you can achieve the 500MHz. The F max specification is based on the fast clock used for serial data. T he interface F max is also dependent on the parallel clock domain which is design dependent and requires timing analysis. Hope this clarified. Regards, Wincent_Intel Replies: Re: MCDMA/PCIe - what is frequency of coreclkout_hip? Hi, Sure! This is the PLL configuration And the system view with clock interfaces And this is what clock report with the final snapshot clkout of the IOPLL And clock network report Regards, TN Replies: Re: MCDMA/PCIe - what is frequency of coreclkout_hip? Hi, Can you please provide me the printscreen of the TA report that mentioning 500 MHz ? Regards, Wincent_Intel Replies: Re: MCDMA/PCIe - what is frequency of coreclkout_hip? Hi Wincent, I used the example design provided in Quartus. Running PIO transfer, gencheck, loopback seem OK. Then, I want to insert our accelerators to receive data from the HOST, doing computations, and send back results to the HOST. I want to run these accelerators at a lower frequency (200MHz), so I pulled PLL core which uses coreclkout_hip as the reference clock. But when re-checking TA clock report, it showed the output clock freq = 400 MHz and refclk = 500 MHz @Wincent_Altera wrote: Can you check if you enable two clock together ? Could you clarify this? I could not see where to enable two clocks when pulling the MCDMA IP Core. There is only 1 selection regarding frequency: " PCIe gen3 x8 - 250 MHz " Thanks, TN Replies: Re: MCDMA/PCIe - what is frequency of coreclkout_hip? Hi, The frequency of coreclkout_hip is for gen3x8 is 250 MHz as per mention in the user guide. Are you using the design example provided in Quartus ? Can you check if you enable two clock together ? Regards, Wincent_Intel