MIPI H.265 - The MIPI H.265 IP Core, based on the High Efficiency Video Coding (HEVC) standard, is an advanced video compression solution optimized for ultra-high-definition (UHD) video applications. Agilex™ 5 FPGA D-Series Agilex™ 5 FPGA E-Series Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 7 FPGA M-Series Arria® 10 GT FPGA Arria® 10 GX FPGA Arria® 10 SX FPGA Stratix® 10 AX FPGA Stratix® 10 DX FPGA Stratix® 10 GX FPGA Stratix® 10 SX FPGA Stratix® 10 TX FPGA The MIPI H.265 IP Core, based on the High Efficiency Video Coding (HEVC) standard, is an advanced video compression solution optimized for ultra-high-definition (UHD) video applications. Delivering up to 50% better compression than H.264 at the same visual quality, this IP core enables efficient streaming, transmission, and storage of 4K and 8K video content while reducing bandwidth and power requirements. Audio / Video Aerospace ASIC Proto Consumer Industrial Medical Test Transportation MIPI H.265 Key Features Fully Compliant with HEVC (ITU-T H.265 | ISO/IEC 23008-2): Supports Main, Main 10 profiles up to Level 5.1 Offering Brief No No No Yes Encrypted Verilog Verilog Agilex™ 5 FPGA D-Series Agilex™ 5 FPGA E-Series Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 7 FPGA M-Series Arria® 10 GT FPGA Arria® 10 GX FPGA Arria® 10 SX FPGA Stratix® 10 AX FPGA Stratix® 10 DX FPGA Stratix® 10 GX FPGA Stratix® 10 SX FPGA Stratix® 10 TX FPGA Yes Yes 24.3.1 Offering Brief Production Linux, Android, RTOS with driver support a1JUi000007bAijMAE What's Included Synthesizable RTL source code Ordering Information QB-IP-MIPI-H.265-1 a1JUi000007bAijMAE Production Intellectual Property (IP) Audio / Video a1MUi00000BOWpkMAH a1MUi00000BOWpkMAH Member 2026-03-10T21:13:45.000+0000 The MIPI H.265 IP Core, based on the High Efficiency Video Coding (HEVC) standard, is an advanced video compression solution optimized for ultra-high-definition (UHD) video applications. Partner Solutions