Why do I see a DQS write preamble (tWPRE) violation in hardware when using DDR3 or DDR2 SDRAM hard memory controller with UniPHY? - Why do I see a DQS write preamble (tWPRE) violation in hardware when using DDR3 or DDR2 SDRAM hard memory controller with UniPHY? Description Due to a problem in the Quartus® II software, when using the hard memory controller with UniPHY, a tWPRE timing violation might be observed when probing the signals with an oscilloscope. This issue occurs because the parallel termination circuitry (read OCT) does not switch to series termination mode early enough to prevent squelching of the DQS write preamble. Resolution This problem does not affect hardware operation. Please get in touch with Intel® IPS Support for more details. Custom Fields values: ['novalue'] Troubleshooting 2205754968 False ['External Memory Interfaces Debug Component IP'] ['FPGA Dev Tools Quartus II Software'] novalue 13.0.1 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']