Support logic conflicts with F-tile PMA clocking and double-width 16b (Quartus Pro 22.1) - Support logic conflicts with F-tile PMA clocking and double-width 16b (Quartus Pro 22.1) I tried to set the F-tile: PMA Direct PMA clocking PMA width 16b TX and RX double-width enabled Qsys doesn't complain and I can generate the files. From the user guide, it seems possible: At the Logic generation, I get errors. Error(21843): Conflict 0 ---------------------------------------------------------------- Error(21843): Rule: gdr_wrapper::topology_mapping_mux_rule @ Error(21843): as.sw_topology != UX16E400GPTP_XX_DISABLED_XX_DISABLED || gdr.z1577a.topology == UX16E400GPTP_XX_DISABLED_XX_DISABLED Error(21843): Rule: gdr_virtual_channel::topo_and_stream_down_to_maib_adapter_tx_and_rx_fifo_mode_and_width_rules @ gdr Error(21843): gdr.z1577a.topology != UX16E400GPTP_XX_DISABLED_XX_DISABLED || gdr.z1577a.u_e400g_top.e400g_stream15_tx_en == FALSE || gdr.z1577a.u_e400g_top.e400g_stream15_sys_clk_src != E400G_STREAM15_SYS_CLK_SRC_XCVR || gdr.z1577a.u_e400g_top.e400g_stream15_tx_aib_if_fifo_mode != E400G_STREAM15_TX_AIB_IF_FIFO_MODE_REGISTER || gdr.z1577a.u_e400g_top.e400g_stream15_tx_excvr_if_fifo_mode != E400G_STREAM15_TX_EXCVR_IF_FIFO_MODE_PHASECOMP || gdr.z1577a.u_e400g_top.e400g_stream15_tx_primary_use != E400G_STREAM15_TX_PRIMARY_USE_DIRECT_BUNDLE || gdr.z1577a.u_e400g_top.e400g_stream15_tx_xcvr_width inside {E400G_STREAM15_TX_XCVR_WIDTH_10,E400G_STREAM15_TX_XCVR_WIDTH_20,E400G_STREAM15_TX_XCVR_WIDTH_32} Error(21843): Rule: gdra_gdr_e400g_top::e400g_stream15_sys_clk_src_rule @ gdr.z1577a.u_e400g_top Error(21843): (gdr.z1577a.u_e400g_top.e400g_25g_15_sys_clk_src -> MAC_LOOPBACK.PCSMAC.fgt_10g_single|directphy_f_0|dphy_hip_inst|persystem[0].perehip_rx[0].rx_ehip.x_bb_f_ehip_rx.sys_clk_src) != E400G_25G_15_SYS_CLK_SRC_XCVR || (gdr.z1577a.u_e400g_top.e400g_25g_15_tx_en -> MAC_LOOPBACK.PCSMAC.fgt_10g_single|directphy_f_0|dphy_hip_inst|persystem[0].perehip_tx[0].tx_ehip.x_bb_f_ehip_tx.tx_en) == FALSE || gdr.z1577a.u_e400g_top.e400g_stream15_sys_clk_src== E400G_STREAM15_SYS_CLK_SRC_XCVR Error(21843): Rule: gdra_gdr_e400g_top::e400g_stream15_tx_aib_if_fifo_mode_rule @ gdr.z1577a.u_e400g_top Error(21843): (gdr.z1577a.u_e400g_top.e400g_25g_15_tx_en -> MAC_LOOPBACK.PCSMAC.fgt_10g_single|directphy_f_0|dphy_hip_inst|persystem[0].perehip_tx[0].tx_ehip.x_bb_f_ehip_tx.tx_en) == FALSE || (gdr.z1577a.u_e400g_top.e400g_25g_15_tx_aib_if_fifo_mode -> MAC_LOOPBACK.PCSMAC.fgt_10g_single|directphy_f_0|dphy_hip_inst|persystem[0].perehip_tx[0].tx_ehip.x_bb_f_ehip_tx.tx_aib_if_fifo_mode) != E400G_25G_15_TX_AIB_IF_FIFO_MODE_REGISTER || gdr.z1577a.u_e400g_top.e400g_stream15_tx_aib_if_fifo_mode == E400G_STREAM15_TX_AIB_IF_FIFO_MODE_REGISTER Error(21843): Rule: gdra_gdr_e400g_top::e400g_stream15_tx_enable_rule @ gdr.z1577a.u_e400g_top Error(21843): (gdr.z1577a.u_e400g_top.e400g_25g_15_tx_primary_use -> MAC_LOOPBACK.PCSMAC.fgt_10g_single|directphy_f_0|dphy_hip_inst|persystem[0].perehip_tx[0].tx_ehip.x_bb_f_ehip_tx.tx_primary_use) == E400G_25G_15_TX_PRIMARY_USE_DISABLED || gdr.z1577a.u_e400g_top.e400g_stream15_tx_en == TRUE Error(21843): Rule: gdra_gdr_e400g_top::e400g_stream15_tx_excvr_if_fifo_mode_rule @ gdr.z1577a.u_e400g_top Error(21843): (gdr.z1577a.u_e400g_top.e400g_25g_15_tx_en -> MAC_LOOPBACK.PCSMAC.fgt_10g_single|directphy_f_0|dphy_hip_inst|persystem[0].perehip_tx[0].tx_ehip.x_bb_f_ehip_tx.tx_en) == FALSE || (gdr.z1577a.u_e400g_top.e400g_25g_15_tx_excvr_if_fifo_mode -> MAC_LOOPBACK.PCSMAC.fgt_10g_single|directphy_f_0|dphy_hip_inst|persystem[0].perehip_tx[0].tx_ehip.x_bb_f_ehip_tx.tx_excvr_if_fifo_mode) != E400G_25G_15_TX_EXCVR_IF_FIFO_MODE_PHASECOMP || gdr.z1577a.u_e400g_top.e400g_stream15_tx_excvr_if_fifo_mode == E400G_STREAM15_TX_EXCVR_IF_FIFO_MODE_PHASECOMP Error(21843): Rule: gdra_gdr_e400g_top::e400g_stream15_tx_primary_use_rule @ gdr.z1577a.u_e400g_top Error(21843): (gdr.z1577a.u_e400g_top.e400g_25g_15_tx_en -> MAC_LOOPBACK.PCSMAC.fgt_10g_single|directphy_f_0|dphy_hip_inst|persystem[0].perehip_tx[0].tx_ehip.x_bb_f_ehip_tx.tx_en) == FALSE || (gdr.z1577a.u_e400g_top.e400g_25g_15_tx_primary_use -> MAC_LOOPBACK.PCSMAC.fgt_10g_single|directphy_f_0|dphy_hip_inst|persystem[0].perehip_tx[0].tx_ehip.x_bb_f_ehip_tx.tx_primary_use) != E400G_25G_15_TX_PRIMARY_USE_DIRECT_BUNDLE || gdr.z1577a.u_e400g_top.e400g_stream15_tx_primary_use == E400G_STREAM15_TX_PRIMARY_USE_DIRECT_BUNDLE Error(21843): Rule: gdra_gdr_e400g_top::e400g_stream15_tx_xcvr_width_rule @ gdr.z1577a.u_e400g_top Error(21843): (gdr.z1577a.u_e400g_top.e400g_25g_15_tx_en -> MAC_LOOPBACK.PCSMAC.fgt_10g_single|directphy_f_0|dphy_hip_inst|persystem[0].perehip_tx[0].tx_ehip.x_bb_f_ehip_tx.tx_en) == FALSE || (gdr.z1577a.u_e400g_top.e400g_25g_15_tx_xcvr_width -> MAC_LOOPBACK.PCSMAC.fgt_10g_single|directphy_f_0|dphy_hip_inst|persystem[0].perehip_tx[0].tx_ehip.x_bb_f_ehip_tx.tx_xcvr_width) != E400G_25G_15_TX_XCVR_WIDTH_16 || gdr.z1577a.u_e400g_top.e400g_stream15_tx_xcvr_width == E400G_STREAM15_TX_XCVR_WIDTH_16 Error(21843): Input variables: Error(21843): as.sw_topology == UX16E400GPTP_XX_DISABLED_XX_DISABLED Error(21843): user.bb_f_ehip_tx[0] -> MAC_LOOPBACK.PCSMAC.fgt_10g_single|directphy_f_0|dphy_hip_inst|persystem[0].perehip_tx[0].tx_ehip.x_bb_f_ehip_tx Error(21843): is_used == TRUE Error(21843): location == E400G_25G_15 Error(21843): sys_clk_src== SYS_CLK_SRC_XCVR Error(21843): tx_aib_if_fifo_mode == TX_AIB_IF_FIFO_MODE_REGISTER Error(21843): tx_en == TRUE Error(21843): tx_excvr_if_fifo_mode == TX_EXCVR_IF_FIFO_MODE_PHASECOMP Error(21843): tx_primary_use == TX_PRIMARY_USE_DIRECT_BUNDLE Error(21843): tx_xcvr_width == TX_XCVR_WIDTH_16 The problem is gdr.z1577a.u_e400g_top.e400g_stream15_tx_xcvr_width inside {E400G_STREAM15_TX_XCVR_WIDTH _10 ,E400G_STREAM15_TX_XCVR_WIDTH _20 ,E400G_STREAM15_TX_XCVR_WIDTH _32 } tx_xcvr_width == TX_XCVR_WIDTH_16 doesn't seem to be allowed. Quartus Pro 22.1 and please find attached the ip file. Is it a bug? Regards, Replies: Re: Support logic conflicts with F-tile PMA clocking and double-width 16b (Quartus Pro 22.1) Hi, We do not receive any response from you to the previous reply that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you Kshitij Goel Replies: Re: Support logic conflicts with F-tile PMA clocking and double-width 16b (Quartus Pro 22.1) Hi, Have you tried with changing the width to 32, It should be able to compile. Thank you Replies: Re: Support logic conflicts with F-tile PMA clocking and double-width 16b (Quartus Pro 22.1) Hi, You can change the width to 32 from 16 in the F-Tile PMA/FEC Direct PHY Intel FPGA IP and then it will get compiled. Sharing the screenshot. Thank you Kshitij Goel Replies: Re: Support logic conflicts with F-tile PMA clocking and double-width 16b (Quartus Pro 22.1) Using the F-tile clocking tool excel file ( https://community.intel.com/t5/FPGA-Intellectual-Property/F-tile-excel-file-Error-Page-Not-Found/m-p/1394117#M25857 ) Replies: Re: Support logic conflicts with F-tile PMA clocking and double-width 16b (Quartus Pro 22.1) Find attached the qar of the project. Regards, Replies: Re: Support logic conflicts with F-tile PMA clocking and double-width 16b (Quartus Pro 22.1) Please confirm the IP is valid and that the settings are allowed. Regards, Replies: Re: Support logic conflicts with F-tile PMA clocking and double-width 16b (Quartus Pro 22.1) Hi, This is only IP, can you please the complete project(.qar) to reproduce the issue. Thank you Kshitij Goel Replies: Re: Support logic conflicts with F-tile PMA clocking and double-width 16b (Quartus Pro 22.1) Hi @Kshitij_Intel , The IP is in my first message, could you confirm the IP's configuration is allowed. Regards, Replies: Re: Support logic conflicts with F-tile PMA clocking and double-width 16b (Quartus Pro 22.1) Hi, Can you please share your .qar. Thank you Kshitij Goel Replies: Re: Support logic conflicts with F-tile PMA clocking and double-width 16b (Quartus Pro 22.1) As per the user guide, actually it seems 16b isn't allowed for double-width. (also 10b even though the support logic would accept it)