Why does Mentor* ModelSim simulation of the Intel® FPGA Triple-Speed Ethernet IP core design example run forever? - Why does Mentor* ModelSim simulation of the Intel® FPGA Triple-Speed Ethernet IP core design example run forever? Description Due to a problem in the Intel® Quartus® Prime Pro Edition version 19.2 Software, the Intel® FPGA Triple-Speed Ethernet IP core Design Example MAC 2xTBI PCS E-tile PMA variant, when the " Enable E-tile transcevier dynamic reconfiguration " option is selected, Mentor* Modelsim simulation will run forever. This is due to the Intel® Stratix® 10 E-tile Avalon Memory Map reconfig_clk and reconfig_reset ports not being properly connected in the design example Mentor* Modelsim simulation test bench file. Resolution To work around this problem in existing releases of the Intel® Quartus® Prime Pro Edition of software, modify the following Mentor* Modelsim test bench files <tse_design_example>\testbench_verilog\<tse_example_design>\eth_tse_0_testbench_tb.v <tse_design_example>\testbench_vhdl\<tse_design_example>\eth_tse_0_testbench_tb.vhd Declare the following Avalon-MM reconfig ports as wires ( wire reconfig_clk_0, wire reconfig_reset_0, wire [18:0] reconfig_address_0, wire reconfig_write_0, wire [7:0] reconfig_writedata_0, wire reconfig_read_0, wire [7:0] reconfig_readdata_0 and wire reconfig_waitrequest_0 ) Assign reg_clk in the testbench to reconfig_clk_0 and reset in the testbench to reconfig_reset_0 . Tie the following signals to 0: reconfig_address_0, reconfig_write_0, reconfig_writedata_0 and reconfig_read_0 . This problem is fixed starting from the Intel® Quartus® Prime Pro Edition v20.3 software. Custom Fields values: ['novalue'] Troubleshooting 1508053921 True ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 20.3 19.2 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']