Why do SD/eMMC operations fail in U-Boot socfpga_v2025.10 and earlier when acting on physical memory address ranges above 4GB in devices with DW‑MMC controller in DMA mode? - Why do SD/eMMC operations fail in U-Boot socfpga_v2025.10 and earlier when acting on physical memory address ranges above 4GB in devices with DW‑MMC controller in DMA mode? Description Due to a limitation in the DW-MMC DMA engine to handle memory address ranges above the 32-bit address space (4GB), the SD/eMMC U-Boot operations acting on these memory ranges may fail, returning an error. The DMA mode was the default mode in the U-Boot socfpga_v2025.10 and earlier. An example of this problem can be observed in the Agilex™ 7 FPGA device when you try to read a file that is too large to be loaded in the low SDRAM memory region (0x00000000 - 0x80000000), so it needs to be loaded in the high region (0x2_80000000 - 0x4_00000000): SOCFPGA # mmc read 0x280000000 0 1000 MMC read: dev # 0, block # 0, count 4096 ... 0 blocks read: ERROR This problem affects all devices that integrate the DW-MMC controller, including Agilex™ 7 FPGA, Arria® 10 FPGA , N5X™, and Stratix® 10 FPGA devices. This problem is only observed when the DW-MMC controller is used in DMA mode. Resolution To workaround this problem, the DW-MMC controller needs to be configured in FIFO PIO mode through the device tree configuration as shown next: &mmc { fifo-mode; }; This problem will be fixed in a future release for all affected devices. Custom Fields values: ['novalue'] Troubleshooting 14027065259 novalue ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 25.3.1 ['Agilex™ 7 FPGAs and SoCs', 'Arria® 10 FPGAs and SoCs', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']