Why do the DDR4 memory interface signals show values of ‘hxx in the waveforms of the example testbench simulation? - Why do the DDR4 memory interface signals show values of ‘hxx in the waveforms of the example testbench simulation? Description You may see values of ‘hxx in the waveforms of the memory interface signals during RTL simulation because initializing the memory content is not supported. Resolution As a workaround, verbose messages can be displayed to indicate memory writes and reads during RTL simulation by enabling the following: Prior to the Quartus® Prime Software Pro version 18.0, override the parameter ‘DIAG_VERBOSE_IOAUX’ to a value of 1 in the DDR4 IP generated ‘mem_array_abphy’ file. In the Quartus® Prime Software Pro version 18.0 and later, enable the Show verbose simulation debug messages option under the Diagnostics tab of the DDR4 IP. Alternatively, override the parameter ‘MEM_ABPHY_VERBOSE’ to a value of 1 in the DDR4 IP-generated ‘mem_array_abphy’ file. In the Quartus® Prime Software Standard version, the verbose messages are always enabled and displayed. If the Abstract phy for fast simulation option under the Diagnostics tab of the DDR4 IP is enabled, then the external memory model is not used in both the Quartus® Prime Software Pro and Standard versions. Therefore, the memory interface signals will always show values of ‘hxx in the waveforms for the Abstract PHY simulations. Custom Fields values: ['novalue'] Troubleshooting 0 False ['External Memory Interfaces Arria® 10 FPGA IP', 'External Memory Interfaces Stratix® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 17.1.1 ['Arria® 10 FPGAs and SoCs', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']