VHDL Basics - Same Course in Japanese: VHDL 基礎編 Same Course in Simplified Chinese: VHDL基础 92 Minutes This online course will provide you with an overview of the VHDL language and its use in logic design. By the end of the course, you will understand the basic parts of a VHDL model and how each is used. You will also gain an understanding of the basic VHDL constructs used in both the synthesis and simulation environments. You will also be able to build complete logic structures that can be synthesized into programmable logic device hardware. Lastly, you gain the understanding required to connect entire models together to create hierarchical designs. Course Objectives At course completion, you will be able to: Understand the simulation versus Synthesis environment use VHDL design units including entities, architectures, configurations and packages Build VHDL Models using language constructs such as assignment statements, process statements, if statements, case statements and loops Create synthesizable Models (behavioral coding style) use VHDL Component instantiations to Create hierarchy (structural coding style) Skills Required Background in digital logic design Prior knowledge of a programming language (e.g., "C" language) is a plus If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OHDL1110. FPGA_OHDL1110. <p>VHDL Basics</p>