Can a dqs bus contention occur when accessing more than one DDR memory using the Altera DDR SDRAM Controller v1.2.0? - Can a dqs bus contention occur when accessing more than one DDR memory using the Altera DDR SDRAM Controller v1.2.0? Description Yes. If performing back to back read accesses where the chip select changes between the accesses and the row in the second CS is already open, then there is the potential for a bus contention. Below is a situation where contention can occur where ACT = Activate and RD = READ: DDR Side ACT A RD A ACT B RD B RD A Local Side read row A in CS1 read row B in CS2 read row A in CS1 The controller recognises that on the second read to row A, the row is already open. Therefore no ACT is necessary. Below is a diagram showing the dqs signals that accompany the read data as it returns from the memory to the FPGA (at the point where RD B is followed immediately by RD A). The result is that the read from CS2 could be lost. The solution is to insert a NOP as follows: DDR Side ACT A RD A ACT B RD B NOP RD A Local Side read row A in CS1 read row B in CS2 nop (de-assert the request for 1 cycle) read row A in CS1 For v1.2.0 of the Altera DDR SDRAM Controller core this must be done by the user. For v2.0 of the core this will be done automatically, becoming transparent to the user. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Stratix® FPGAs'] ['novalue'] ['novalue'] ['novalue']