Do I need to provide a REFCLK_GXE clock signal for unused transceiver E-Tiles to meet Intel® Stratix® 10 & Intel Agilex® 7 FPGA device configuration requirements? - Do I need to provide a REFCLK_GXE clock signal for unused transceiver E-Tiles to meet Intel® Stratix® 10 & Intel Agilex® 7 FPGA device configuration requirements? Description The need for a REFCLK_GXE clock signal for unused transceiver E-Tiles to meet Intel® Stratix® 10 & Intel Agilex® 7 FPGA device configuration requirements depends on whether you preserve your E-Tile transceivers with the PRESERVE_UNUSED_XCVR_CHANNELS Quartus® Settings File (QSF) assignment. Resolution If you never plan to use the transceiver E-Tile and you do not have a PRESERVE_UNUSED_XCVR_CHANNELS QSF assignment, you do not need to provide a REFCLK_GXE signal to meet Intel® Stratix® 10 & Intel Agilex® 7 FPGA device configuration rules. If your current E-Tile is unused, but you plan to use it later, a PRESERVE_UNUSED_XCVR_CHANNELS QSF assignment is required. In this case, you must provide a REFCLK_GXE signal to meet Intel® Stratix® 10 & Intel Agilex® 7 FPGA device configuration rules. Custom Fields values: ['novalue'] Troubleshooting 18017306477 False ['Stratix® 10 E-Tile Transceiver Native PHY'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix No plan to fix ['Agilex™ 7 FPGAs and SoCs', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']