Why do I see hold-time violations when using more than one instance of an Stratix® 10 E-Tile device transceiver IP? - Why do I see hold-time violations when using more than one instance of an Stratix® 10 E-Tile device transceiver IP? Description You may see hold-time violations caused by uncut false paths when using more than one instance of an Stratix® 10 E-tile device transceiver IP. The hold-time violations involve AIB registers clocked from two independent transceiver IP instances. The IP’s should apply false paths between multiple channels within an IP, but you must apply false path SDC constraints between multiple transceiver IP. Resolution To work around this problem, you can apply set_false_path constraints in your top level SDC file. The example below demonstrates how you can apply a false path between two nodes of unrelated transceiver IP Ignore Path: set aib_tx_internal_div_reg_col [get_registers -nowarn nphy_instance_1 .xcvr_client_inst|xcvr_native_s10_etile_0|g_xcvr_native_insts[0].ct3_xcvr_native_inst|inst_ct3_xcvr_channel|inst_ct1_hssi_pldadapt_tx~aib_tx_internal_div.reg] set aib_fabric_transfer_clk_col [get_registers -nowarn nphy_instance_2 .xcvr_client_inst|xcvr_native_s10_etile_0|g_xcvr_native_insts[0].ct3_xcvr_native_inst|inst_ct3_xcvr_channel|inst_ct1_hssi_pldadapt_tx~s2_6_0__aibadpt__aib_fabric_tx_transfer_clk.reg] Next Step: Set False Path set_false_path -from aib_tx_internal_div_reg_col -to aib_fabric_transfer_clk_col Custom Fields values: ['novalue'] Troubleshooting 22010730498 False ['Stratix® 10 E-Tile Transceiver Native PHY'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 19.4 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']